STM32 on moth site

dshot timer setup

Fri, 27 Mar 2026 12:08:37 -0400

I spent most of my week helping another shop member set up for RP2040 programming, as well as brainstorming and developing a plan for their project for robotic arm control.

I also helped several other students use the laser cutter to create acrylic etchings.

As such my work was relatively limited.

It can generally be summarized as follows:

 setup_dshot_timer(TIM1);
 setup_dshot_timer(TIM8);

 configure_dshot_timer_dma(DMA2_Stream5, TIM1, cmd_ccr_tim1_buf[cmd_ccr_front],
 6);
 configure_dshot_timer_dma(DMA2_Stream1, TIM8, cmd_ccr_tim8_buf[cmd_ccr_front],
 7);

 enable_pwm_pins();

 // Set DShot pins OSPEEDR value to high [DS8626 Table 50]
 GPIOA->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED8_Msk | GPIO_OSPEEDR_OSPEED9_Msk |
 GPIO_OSPEEDR_OSPEED10_Msk | GPIO_OSPEEDR_OSPEED11_Msk);
 GPIOA->OSPEEDR |=
 (2 << GPIO_OSPEEDR_OSPEED8_Pos) | (2 << GPIO_OSPEEDR_OSPEED9_Pos) |
 (2 << GPIO_OSPEEDR_OSPEED10_Pos) | (2 << GPIO_OSPEEDR_OSPEED11_Pos);

 GPIOC->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED6_Msk | GPIO_OSPEEDR_OSPEED7_Msk |
 GPIO_OSPEEDR_OSPEED8_Msk | GPIO_OSPEEDR_OSPEED9_Msk);
 GPIOC->OSPEEDR |=
 (2 << GPIO_OSPEEDR_OSPEED6_Pos) | (2 << GPIO_OSPEEDR_OSPEED7_Pos) |
 (2 << GPIO_OSPEEDR_OSPEED8_Pos) | (2 << GPIO_OSPEEDR_OSPEED9_Pos);

setup_dshot_timer() and configure_dshot_timer_dma() simply reduce some code duplication and make the main function easier to read.

Finished RX DMA Setup and Interrupt, Set Hardware NSS

Mon, 23 Mar 2026 10:36:48 -0400

I first finished the SPI RX DMA setup. I simply changed a few settings, and actually included the arming of both streams.

// Reset Stream
 DMA1_Stream3->CR = 0;
 while (DMA1_Stream3->CR & DMA_SxCR_EN);

 // Set source peripheral pointer
 DMA1_Stream3->PAR = (uint32_t)&SPI2->DR;
 // Set buffer pointer
 DMA1_Stream3->M0AR = (uint32_t)cmd_data_buf;
 // Transfer 11 bytes
 DMA1_Stream3->NDTR = 11;
 // Enabled direct mode (no FIFO)
 DMA1_Stream3->FCR = 0;

 DMA1_Stream3->CR =
 DMA_SxCR_TCIE // Enable transfer complete interrupt
 | (0 << DMA_SxCR_DIR_Pos) // Peripheral to Memory
 | DMA_SxCR_MINC // Enable memory increment mode
 | (0 << DMA_SxCR_PSIZE_Pos) // Set 8-bit peripheral data size
 | (0 << DMA_SxCR_MSIZE_Pos) // Set 8-bit memory data size
 // Set priority level to medium. Doesn't actually matter since TIMs and
 // IDR are on on DMA2
 | (1 << DMA_SxCR_PL_Pos) |
 (0 << DMA_SxCR_CHSEL_Pos); // Set channel 0 [RM0090 Table 43]

 DMA1_Stream4->CR = 0;
 while (DMA1_Stream4->CR & DMA_SxCR_EN);

 // Set source periphal pointer
 DMA1_Stream4->PAR = (uint32_t)&SPI2->DR;
 // Set buffer pointer
 DMA1_Stream4->M0AR = (uint32_t)erpm_data_buf;
 // Transfer 11 bytes
 DMA1_Stream4->NDTR = 11;
 // Enable direct mode (no FIFO)
 DMA1_Stream4->FCR = 0;

 DMA1_Stream4->CR =
 (1 << DMA_SxCR_DIR_Pos) // Memory to Peripheral
 | DMA_SxCR_MINC // Enable memory increment mode
 | (0 << DMA_SxCR_PSIZE_Pos) // Set 8-bit peripheral data size
 | (0 << DMA_SxCR_MSIZE_Pos) // Set 8-bit memory data size
 // Set priority level to medium. Doesn't actually
 // matter since TIMs and IDR are on on DMA2
 | (1 << DMA_SxCR_PL_Pos) |
 (0 << DMA_SxCR_CHSEL_Pos); // Set channel 0 [RM0090 Table 43]

 // Arm both streams
 DMA1_Stream3->CR |= DMA_SxCR_EN;
 DMA1_Stream4->CR |= DMA_SxCR_EN;
}

After examining the protocol for re-syching after a CRC failure and looking at methods for frame synchronization I decided to change to hardware NSS, which required some changes to the SPI and PIN setup. I also finished the CRC setup int he SPI configuration, selecting the 0x2F polynomial to allow for triple bit error detection.

more register-level STM32: SPI, DMA, DShot

Fri, 13 Mar 2026 10:37:57 -0400

This is my second attempt at this post, so it’ll probably be a bit shorter than the first time.

I first realized that the HAL_Init() function in the code autogenerated by STM32CubeMX actually does more than just initializing the HAL, it sets up flash, and the SysTick interrupt.

When setting up the flash, I needed to set the proper flash latency for the CPU speed and voltage. Consulting the table, I found 5 to be the correct option.

ESC specification mistakes, correcting r & d, register-level STM32 motor controller implementation

Fri, 06 Mar 2026 07:38:15 -0500

After getting my custom PIO DShot implementation working last week, I needed to someone run the motor in reverse as well as forward. Checking the DShot specification, I needed to send the correct command. These commands occupy the lower 48 values of the 11 bits of data in a DShot packet.

| Number | Command | Remark | |// Set priority level to medium. // matter since TIMS and IDR on DMA2 ————— | ————— | ————— | | 0..6 | … | … | | 7 | DSHOT_CMD_SPIN_DIRECTION_1 | Needs 6x | | 8 | DSHOT_CMD_SPIN_DIRECTION_2 | Needs 6x | | 9 | DSHOT_CMD_3D_MODE_OFF | Needs 6x | | 10 | DSHOT_CMD_3D_MODE_ON | Needs 6x | | 11..47 | … | … |