Finished RX DMA Setup and Interrupt, Set Hardware NSS

Mon, 23 Mar 2026 10:36:48 -0400

I first finished the SPI RX DMA setup. I simply changed a few settings, and actually included the arming of both streams.

// Reset Stream
 DMA1_Stream3->CR = 0;
 while (DMA1_Stream3->CR & DMA_SxCR_EN);

 // Set source peripheral pointer
 DMA1_Stream3->PAR = (uint32_t)&SPI2->DR;
 // Set buffer pointer
 DMA1_Stream3->M0AR = (uint32_t)cmd_data_buf;
 // Transfer 11 bytes
 DMA1_Stream3->NDTR = 11;
 // Enabled direct mode (no FIFO)
 DMA1_Stream3->FCR = 0;

 DMA1_Stream3->CR =
 DMA_SxCR_TCIE // Enable transfer complete interrupt
 | (0 << DMA_SxCR_DIR_Pos) // Peripheral to Memory
 | DMA_SxCR_MINC // Enable memory increment mode
 | (0 << DMA_SxCR_PSIZE_Pos) // Set 8-bit peripheral data size
 | (0 << DMA_SxCR_MSIZE_Pos) // Set 8-bit memory data size
 // Set priority level to medium. Doesn't actually matter since TIMs and
 // IDR are on on DMA2
 | (1 << DMA_SxCR_PL_Pos) |
 (0 << DMA_SxCR_CHSEL_Pos); // Set channel 0 [RM0090 Table 43]

 DMA1_Stream4->CR = 0;
 while (DMA1_Stream4->CR & DMA_SxCR_EN);

 // Set source periphal pointer
 DMA1_Stream4->PAR = (uint32_t)&SPI2->DR;
 // Set buffer pointer
 DMA1_Stream4->M0AR = (uint32_t)erpm_data_buf;
 // Transfer 11 bytes
 DMA1_Stream4->NDTR = 11;
 // Enable direct mode (no FIFO)
 DMA1_Stream4->FCR = 0;

 DMA1_Stream4->CR =
 (1 << DMA_SxCR_DIR_Pos) // Memory to Peripheral
 | DMA_SxCR_MINC // Enable memory increment mode
 | (0 << DMA_SxCR_PSIZE_Pos) // Set 8-bit peripheral data size
 | (0 << DMA_SxCR_MSIZE_Pos) // Set 8-bit memory data size
 // Set priority level to medium. Doesn't actually
 // matter since TIMs and IDR are on on DMA2
 | (1 << DMA_SxCR_PL_Pos) |
 (0 << DMA_SxCR_CHSEL_Pos); // Set channel 0 [RM0090 Table 43]

 // Arm both streams
 DMA1_Stream3->CR |= DMA_SxCR_EN;
 DMA1_Stream4->CR |= DMA_SxCR_EN;
}

After examining the protocol for re-syching after a CRC failure and looking at methods for frame synchronization I decided to change to hardware NSS, which required some changes to the SPI and PIN setup. I also finished the CRC setup int he SPI configuration, selecting the 0x2F polynomial to allow for triple bit error detection.

DMA on moth site

Finished RX DMA Setup and Interrupt, Set Hardware NSS